The present invention relates to a Josephson memory circuit using Josephson gates and, more particularly, to a Josephson NDRO (NONDESTRUCTIVE READOUT) memory circuit adapted to store binary information represented by the presence/absence or direction of a persistent circulating current which is to flow through a superconducting loop having a Josephson gate therein.
In the past, some Josephson memory circuits have been proposed which feature a short access time and low power consumption. Typical of such Josephson memories may be the one described in a paper by W. H. Henkels entitled "Fundamental criteria for the design of high-performance Josephson nondestructive readout random access memory cells and experimental confirmation", J. Appl. Phys. 50 (12), December 1979, pp. 8143-8168, or the one described in a paper by W. H. Henkels and J. H. Greiner entitled "Experimental Single Flux Quantum NDRO Josephson Memory Cell," IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, No. 5, October 1979, pp. 794-796.
Basically, a Josephson memory circuit of the type described consists of cells arranged in a matrix. Each of the cells comprises a superconducting closed loop having one Josephson write gate therein and a Josephson sense gate which is disposed near the superconducting loop. The superconducting loops of the cells in the column direction are respectively connected in series through bias lines. Two independent control lines extend in the vicinity of the write gates in the row and column directions, respectively, in order to apply control magnetic fields to the write gates. A sense line is associated with the sense gate of each cell in the row direction so as to permit a read bias current to flow therethrough.
To write information into a cell, predetermined levels of currents are supplied to the bias line and the two control lines associated with the cell. The currents thus supplied allow the write gate to temporarily have a voltage state of a certain level (referred to hereunder as "voltage state") so that the bias current flows through one branch of the superconducting loop which does not include the write gate. Thereafter, the supply of the currents is cut off to hold in the superconducting loop a persistent circulating current which flows toward the above-mentioned one branch. To remove the circulating current, two control currents are supplied without supplying the bias current, so that the write gate is brought to the voltage state and the supply of the currents is interrupted.
For reading information out of the cell, the control characteristic of the sense gate is selected so that the sense gate is switched to the zero-voltage state or to the voltage state by a magnetic field due to the bias current which flows through the previously mentioned one branch in response to coincidence of the bias current and the read bias current, or by a magnetic field due to the sum of the bias current, the read bias current and the circulating current. Thus, information is read out by detecting a state of the sense gate.
As described above, however, the prior art Josephson memory circuit has a complicated construction because every cell needs one bias line, two control lines and one sense line and each of these lines must be provided with a power source. This is objectionable in the aspects of integration density, yield and uniformity in the characteristics of the products.